library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity sumNb_2 is
	generic(
		N: natural := 4
	);
	port(
		a_i	: in std_logic_vector(N-1 downto 0);
		b_i	: in std_logic_vector(N-1 downto 0);
		ci_i: in std_logic;
		s_o	: out std_logic_vector(N-1 downto 0);
		co_o: out std_logic
	);
end;

architecture sumNb_2_arq of sumNb_2 is
	
	-- signal a_aux: std_logic_vector(N+1 downto 0);
	-- signal b_aux: std_logic_vector(N+1 downto 0);
	signal s_aux: std_logic_vector(N+1 downto 0);

begin
	-- a_aux <= '0' & a_i & ci_i;
	-- b_aux <= '0' & b_i & '1';
	-- s_aux <= std_logic_vector(unsigned(a_aux) + unsigned(b_aux));
	
	s_aux <= std_logic_vector(unsigned('0' & a_i & ci_i) + unsigned('0' & b_i & '1'));

	s_o <= s_aux(N downto 1);
	co_o <= s_aux(N+1);

end;